Semiconductor integrated circuit, operating state detector, and electronic equipment

ABSTRACT

The present invention relates to a semiconductor integrated circuit having function blocks with differing operating frequencies and to a semiconductor integrated circuit wherein the threshold voltages of MOS transistors that configure these function blocks are different for each function block. In first to Nth function blocks ( 30 - 1  to  30 -N), which are supplied with constant voltages (V C1  to V CN ) generated by a constant voltage generation section ( 20 ) as power voltages, any variation in operating speed or in the capability of the transistors is detected by an operating state detector ( 40 ) as a voltage (V fre ). Further, an operating state encoding section ( 50 ) encodes the voltage (V fre ), a voltage output control section ( 60 ) modifies basic voltages (V B1  to V BN ) of the constant voltage generation section ( 20 ), and constant voltages (V C1  to V CN ) for the function blocks ( 30 - 1  to  30 -N) is modified.

TECHNICAL FIELD

[0001] The present invention relates to an improvement in asemiconductor integrated circuit and electronic equipment using thesame, comprising a constant voltage generation section that increases ordecreases a power voltage supplied from an external power source togenerate a constant voltage, and a function block that uses the constantvoltage generated from the constant voltage generation section as apower source.

BACKGROUND OF ART

[0002] An example of this type of semiconductor integrated circuit isshown in FIG. 11. In FIG. 11, a reference power voltage 2 obtained froman external power source 1 is supplied to a constant voltage generationdevice 3. The constant voltage generation device 3 generates a fixedconstant voltage 4, based on the reference power voltage 2, and suppliesit as a power voltage to first and second function blocks 6A and 6B. Thefirst and second function blocks 6A and AB convert any input signals 5Aand AB based on corresponding specific functions, to generated outputsignals 7A and AB having specific functions. When the first and secondfunction blocks 6A and AB are in a standby state, the operation of thecorresponding first and second function blocks 6A and 6B is halted andthe current supplied from the output constant voltage 4 is reduced bysuppressing the signals 5A and AB by function stop signals 8A and AB.

[0003] With a conventional semiconductor integrated circuit, theconstant voltage 4 is necessary for enabling response at the highestoperating speed for all operating states for converting any inputsignals 5A and AB to specific functions.

[0004] However, when the constant voltage 4 is supplied at the highestoperating speed in all of the operating states of the first and secondfunction blocks 6A and AB, even if it is necessary for one functionblock 5A to operate at the highest speed, it could happen that such anoperating speed is not required for the other function block 5B. As acase in which the difference between the highest operating speed and thelowest operating speed in operation is extremely large, it is possibleto consider that a data access circuit and a frequency converter areused in common within the semiconductor integrated circuit.

[0005] If prior-art techniques are used, a high power voltagecorresponding to the highest response speed will be necessary for onefunction block 6A in such a case, and it is not possible to control thepower consumption.

[0006] With prior-art techniques, although it is possible to reduce theoperating current on standby, a large amount of operating current isconsumed during operation when the semiconductor integrated circuitcontains at least two circuits having different operating speedrespectively and there is an extremely large difference between thehighest operating speed and the lowest operating speed while in theoperating state, because the power voltage while in the operating stateis supplied as a voltage level at a signal response that is enabled bythe highest operating speed of the function blocks. It is thereforedifficult to guarantee the circuit response speed at both the highestoperating speed and the lowest operating speed necessary for thefunction blocks, while simultaneously implementing a reduction in powercurrent.

[0007] The MOS transistors that configure the plurality of functionblocks often have different threshold voltages, due to unevenness in thesemiconductor wafer surface during the manufacturing process. Thisraises a technical problem in that the frequency response speeds will bedifferent for each function block, even if the same power voltage issupplied to all of the function blocks operating at the same speed.

[0008] An objective of the present invention is to provide asemiconductor integrated circuit and electronic equipment using the samewhich solve the previously described technical problems and make itpossible to reduce the operating current flowing during operation andthus reduce the power consumption, even if there are at least twocircuits, which have different operating speed respectively, coexistingwithin the semiconductor integrated circuit, and the difference betweenthe highest operating speed and the lowest operating speed is extremelylarge.

[0009] Another objective of the present invention is to provide asemiconductor integrated circuit and electronic equipment using the samewhich make it possible to reduce variations in the frequency responsespeeds of a plurality of function blocks, even when the manufacturingprocess has created differences in the threshold voltages of MOStransistors configuring those function blocks and the same power voltageis supplied to the function blocks operating at the same operatingspeed.

DISCLOSURE OF INVENTION

[0010] A semiconductor integrated circuit in accordance with the presentinvention comprises:

[0011] at least one constant voltage generation section for increasingor decreasing a power voltage supplied from at least one external powersource, based on a basic voltage, to generate at least one constantvoltage;

[0012] at least one function block to which is supplied the at least oneconstant voltage generated by the at least one constant voltagegeneration section;

[0013] at least one operating state detection section for generating asecond signal indicating an operating state of the at least one functionblock, based on a first signal including operating speed information ofthe at least one function block;

[0014] at least one operating state encoding section for encoding anoperating state of the function block to generate operating state data,based on the second signal; and

[0015] at least one voltage output control section for modifying thebasic voltage of the at least one constant voltage generation section,based on the operating state data.

[0016] The semiconductor integrated circuit of this aspect of theinvention makes it possible to obtain the optimal power voltagenecessary for the operation of the function blocks, based on thegeneration of a second signal indicating the operating state of thesefunction blocks, which in turn is based on a first signal comprisingoperating speed information (the actual operating frequency) of eachfunction block. The semiconductor integrated circuit of the presentinvention also makes it possible to implement the supply of the optimalpower voltage corresponding to the operating speed of each functionblock, even when the threshold voltages of the MOS transistors thereofvary from the design values during the manufacturing process.

[0017] This aspect of the invention makes it possible to achieve theeffect of reducing the power consumption by setting power voltages thatare optimized for the operation of each of the function blocks from asignal period in which rapid operation is necessary to a signal periodin which the response during low-speed operation is sufficient.

[0018] With this aspect of the present invention, an operating-settingsignal is preferably input to each function block, and that functionblock supplies the first signal to the at least one operating statedetection section when the operating-setting signal is active.

[0019] In such a case, the operating-setting signal could be set in sucha manner that it becomes active at timings on the time axis that differfor each of the plurality of function blocks.

[0020] This means that one each of the at least one operating statedetection section, at least one operating state encoding section, atleast one voltage output control section, and at least one constantvoltage generation section can be used in common for the plurality offunction blocks.

[0021] With this aspect of the present invention, the voltage outputcontrol section may comprise a digital-analog converter for performing adigital-to-analog conversion on the operating state data; and asample-and-hold circuit for sampling an output of the digital-analogconverter based on the operating-setting signal, and generating thebasic voltage. This configuration makes it possible to continue to holda proper basic voltage for each function block, to ensure the optimalconstant voltage for each function block.

[0022] With the present invention, the operating state detection sectionmay further comprise an integrator for integrating the first signal; anda peak detector for detecting a peak value of an output of theintegrator, and holding the peak value as the second signal.

[0023] Alternatively, in stead of the above described peak detector, theoperating state detection section of the present invention may furthercomprise a peak-to-peak detector for detecting a voltage amplitude of anoutput of the integrator, and holding the voltage amplitude as thesecond signal.

[0024] This configuration makes it possible to apply negative feedbackaccurately, even when the manufacturing process has changed thethreshold voltages of the P- and N-channel transistors from their designvalues, and there are differences in the amplitude between the rise andfall of the integrator output.

[0025] With the present invention, the operating state encoding sectionmay comprise a plurality of comparators for comparing the voltage levelof the second signal with each of a plurality of reference voltagelevels; and a decoder for encoding outputs of the plurality ofcomparators. This makes it easy to use the second signal for encoding,for providing negative feedback.

[0026] The operating state encoding section of the present invention mayfurther comprise a plurality of voltage-dividing resistors for dividingthe constant voltage from the constant voltage generation section, tocreate the plurality of reference voltage levels.

[0027] This configuration makes it easy to create a preliminary signalwhen encoding is implemented based on the second signal.

[0028] In a semiconductor integrated circuit in accordance with anotheraspect of the present invention, the at least one operating statedetection section is modified into at least one frequency-voltageconverter, and the at least one frequency-voltage converter converts theactual operating frequency of the at least one function block into avoltage level.

[0029] As described previously, a second signal that indicates theoperating state of each function block is generated based on a firstsignal containing the actual operating frequency of that function block,then the optimal power voltage necessary for the operation of thefunction block is obtained therefrom.

[0030] This frequency-voltage converter preferably converts a frequencyof an input signal that is input to the function block into a voltagelevel. This is because the input signal usually contains the maximumfrequency among the signals within the function block, so it reflectsthe actual operating frequency of the function block.

[0031] Since power consumption can be reduced in electronic equipment inaccordance with the present invention, which comprises the abovesemiconductor integrated circuit, it can be applied as appropriate tomany different applications, particularly to timepieces, mobilecomputers, and portable phones.

BRIEF DESCRIPTION OF DRAWINGS

[0032]FIG. 1 is a block diagram of a first embodiment of the presentinvention;

[0033]FIG. 2 is a block diagram showing details of a configuration inwhich a first function block of FIG. 1 is operating as a frequencyconverter and negative feedback is used to modify the constant voltagesupplied to that frequency converter;

[0034]FIG. 3 is a timing chart showing signal waveforms during theprocess of applying negative feedback in the configuration of FIG. 2;

[0035]FIG. 4 is a schematic view illustrating the operation of theoperating state encoding section of FIG. 2;

[0036]FIG. 5 is a timing chart showing signal waveforms during theprocess of using negative feedback to modify the constant voltagesupplied to the second function block;

[0037]FIG. 6 is a timing chart showing signal waveforms during theprocess of using negative feedback to modify the constant voltagesupplied to the Nth function block;

[0038]FIG. 7 is a timing chart of a second embodiment of the presentinvention, showing the signal waveforms during the process of usingnegative feedback to modify the constant voltages supplied to functionblocks to which the same input signal is input, when the thresholdvoltages Vth of the MOS transistors configuring the function blocks ofFIG. 1 are different;

[0039]FIG. 8 is a block diagram of a device in accordance with a thirdembodiment of the present invention;

[0040]FIG. 9 is a timing chart showing signal waveforms during theprocess of using negative feedback to modify the constant voltagesupplied to the plurality of function blocks used in the circuit of FIG.8;

[0041]FIG. 10 is a block diagram of electronic equipment in accordancewith a fourth embodiment of the present invention; and

[0042]FIG. 11 is a block diagram of a prior-art semiconductor integratedcircuit.

BEST MODE FOR CARRYING OUT THE INVENTION

[0043] First Embodiment

[0044] A first embodiment of the present invention is described belowwith reference to FIGS. 1 to 6.

[0045]FIG. 1 is a block diagram of the overall structure of the devicein accordance with an embodiment of the present invention. In FIG. 1,the device of this embodiment comprises an external power source 1 and asemiconductor integrated circuit 10. The semiconductor integratedcircuit 10 comprises a constant voltage generation section 20, first toNth function blocks 30-1 to 30-N, an operating state detector 40, anoperating state encoding section 50, and a voltage output controlsection 60.

[0046] The device of this embodiment is characterized in that constantvoltages V_(C) (V_(C1) to V_(CN)) that are supplied to the first to Nthfunction blocks 30-1 to 30-N, respectively, can be controlled bynegative feedback based on the operating states of the correspondingfirst to Nth function blocks 30-1 to 30-N, in other words, their actualoperating frequencies.

[0047] A power voltage VS that is output from the external power source1 is supplied to the constant voltage generation section 20, where theconstant voltages V_(C1) to V_(CN) are generated with reference to basicvoltages V_(B1) to V_(BN). The constant voltages V_(C1) to V_(CN)generated by the constant voltage generation section 20 are supplied aspower voltages to the corresponding first to Nth function blocks 30-1 to30-N. The first to Nth function blocks 30-1 to 30-N use their specificfunctions to modify corresponding input signals V_(IN1) to V_(INN) andgenerate corresponding output signals V_(OUT1) to V_(OUTN). When theoperation stopping signals S_(STOP1) to S_(STOPN) are non-active (i.e.,are at the 1-state) and the operation determination setting signalsS_(SET1) to S_(SETN) are active (i.e., are at the 1-state), the inputsignals V_(IN1) to V_(INN) that are input to the corresponding first toNth function blocks 30-1 to 30-N are output as the operation signal S1without change to the operating state detector 40.

[0048] When the operation determination setting signals S_(SET1) toS_(SETN) are at the 0-state, the operation signal S1 is not generatedfrom the first to Nth function blocks 30-1 to 30-N. Note that each ofthe operation determination setting signals S_(SET1) to S_(SETN) becomesactive at a different timing on the time axis. Therefore, the operatingstates of the first to Nth function blocks 30-1 to 30-N are detected bythe operating state detector 40 at correspondingly different timings.

[0049] The operating state detector 40 outputs to the operating stateencoding section 50 an operating state signal S2 having a voltageV_(fre) corresponding to the operating states of the first to Nthfunction blocks 30-1 to 30-N, in other words, their actual operatingfrequencies, based on the operation signal S1. This means that theoperating state detector 40 functions as a frequency-voltage converter.

[0050] The operating state encoding section 50 detects the voltageV_(fre) of the operating state signal S2 and generates n-bit digitizedoperating state data D in accordance with voltage level encodinginformation that has been set previously.

[0051] This operating state data D is input to the voltage outputcontrol section 60. The voltage output control section 60 converts theoperating state data D into voltages in accordance with voltagegeneration information that was set previously. These converted voltagesare supplied to the constant voltage generation section 20 as the basicvoltages V_(B1) to V_(BN).

[0052] The constant voltage generation section 20 modifies the levels ofthe constant voltages V_(C1) to V_(CN) forming the power voltages forthe first to Nth function blocks 30-1 to 30-N, based on thethus-supplied basic voltages V_(B1) to V_(BN).

[0053] The description now turns to the operation and a specificconfiguration for modifying and controlling the constant voltage V_(C1)of the first function block 30-1 of FIG. 1 by negative feedback, withreference to FIGS. 2 to 4.

[0054]FIG. 2 is a block diagram of a specific configuration formodifying and controlling the constant voltage V_(C1) of the firstfunction block 30-1 by negative feedback.

[0055] The power voltage VS that is output from the external powersource 1 is supplied to the constant voltage generation section 20,which generates the constant voltage V_(C1) with reference to the basicvoltage V_(B1). This constant voltage generation section 20 comprises anoperational amplifier 22, a transistor Q1, and two resistors R1 and R2.The basic voltage V_(B1) from the voltage output control section 60 isconnected to an inverted-input pin of the operational amplifier 22 andthe connection point between the resistors R1 and R2 is connected to adirect-input pin of the operational amplifier 22. This configurationensures that the operational amplifier 22 and the other components forma negative feedback amplification circuit, such that if the voltage atthe direct-input pin varies with respect to the basic voltage V_(B1) theoutput of the operational amplifier 22 is also changed, ensuring thatthe output of the operational amplifier 22 is stable. The voltage V_(C1)that is output from the constant voltage generation section 20 duringthis stage is given by:

V _(C1) =V _(B1) ×R1/(R1+R 2)

[0056] It is clear that, if the basic voltage V_(B1) varies, theconstant voltage V_(C1) can also be varied in this manner.

[0057] Note that the constant voltage generation section 20 shown inFIG. 2 does not include the circuitry for generating the constantvoltages VC₂ to V_(CN) to be supplied to the second to Nth functionblocks 30-2 to 30-N, based on the basic voltages VB₂ to V_(BN), but inactual practice there will be N negative feedback amplificationcircuits, comprising the operational amplifier 22, the transistor Q1,and the resistors R1 and R2 within the constant voltage generationsection 20. In the state before negative feedback is applied, the basicvoltages V_(B1) to V_(BN) are set to initial voltages.

[0058] The constant voltage V_(C1) that is generated by the constantvoltage generation section 20 is applied as the power voltage to thefirst function block 30-1. The first function block 30-1 modifies anyinput signal S_(IN1) into any frequency to generate the output signalV_(OUT1), by using flip-flops D_(F0) to D_(Fm) and frequency-switchingsignals F_(D0) to F_(Dm), in accordance with setting signals F_(S0) toF_(Sm) and resetting signals F_(R0) to F_(Rm) that are generated by afrequency setting decoder 34.

[0059] The signal S_(IN1) that has been input to the first functionblock 30-1 is input to a logical product gate AND together with thefunction stop signal S_(STOP1) and the input signal S_(IN1) is outputwithout change in the function stop signal S_(STOP1) is non-active, inother words, when it is at the 1-state. When the function stop signalS_(STOP1) is active, in other words, at the 0-state, the logical productgate AND does not transmit the input signal S_(IN1); it controls theinput signal S_(IN1) to be at the 0-state and stops the functioning ofthe first function block 30-1.

[0060] The input signal S_(IN1) that is output when the function stopsignal S_(STOP1) is at the 1-state is output to the operating statedetector 40 (see FIG. 3) as the operation signal S1 through theoperating state transmitter 32, when the operation determination settingsignal S_(SET1) is at the 1-state (period T₁ in FIG. 3). Note that whenthe operation determination setting signal S_(SET1) is in the 0-state,the input signal S_(IN1) is not transferred to the operating statetransmitter 32 and the operation signal S1 remains at the 0-state.

[0061] The operating state detector 40 comprises an integrator 42 and apeak detector 42. The input operation signal S1 is integrated by theintegrator 42 to become an integration signal S_(INTE). The peak valueof this integration signal S_(INTE) is held by the peak detector 44 andthe operating state signal S2 is generated therefrom (see FIG. 3).

[0062] As described previously, the operating state detector 40functions as a frequency-voltage converter for detecting a voltagecorresponding to the actual operating frequency of the first functionblock 30-1, in order to detect the operating state of the first functionblock 30-1. To ensure that the input signal S_(IN1) contains the maximumfrequency of all the signals that are used by the first function block30-1, the configuration is generally such that the operating statedetector 40 of this embodiment integrates the input signal S_(IN1) andholds the peak value thereof. Therefore, the voltage V_(fre) of theoperating state signal S2, which is the output of the operating statedetector 40, is at a level corresponding to the actual operatingfrequency of the first function block 30-1.

[0063] This operating state signal S2 is input to the operating stateencoding section 50. This operating state encoding section 50 comprisesresistors r₀ to r_(n), voltage comparators 52-1 to 52-n, and a decoder54. The resistors r₀ to r_(n) are connected in series and the constantvoltage V_(C1) is applied to the resistor r₀. This constant voltageV_(C1) is divided by the resistors r₀ to r_(n) to generate referencevoltages V_(ref) to V_(refn) at the connection points of respectiveresistors.

[0064] The voltage V_(fre) of the operating state signal S2 is input incommon to the direct-input pins of n voltage comparators 52-1 to 52-n,and the reference voltages V_(ref1) to V_(refn) are input individuallyto the corresponding inverted-input pins thereof.

[0065] Thus the n voltage comparators 52-1 to 52-n compare thecorresponding reference voltages V_(ref1) to V_(refn) with the voltageof the operating state signal S2. This will be described below withreference to FIG. 4. Voltage is plotted along the vertical axis of FIG.4 and if the resistances for the previously described reference voltagesV_(ref1) to V_(refn) are all the same, the relationships between thereference voltages V_(ref1) to V_(refn) are as shown in FIG. 4. If thelevel of the voltage V_(fre) of the operating state signal S2 is V_(P1),as shown in FIG. 4, the outputs of the nvoltage comparators 52-1 to 52-nis expressed as (00001111) if represented in sequence by 1 or 0 for n=8.

[0066] The outputs of these n voltage comparators 52-1 to 52-n are inputto the decoder 54 where they are encoded. The decoder 54 inverts thestring of data (00001111) of the signals input from the n voltagecomparators 52-1 to 52-n, from the most significant bit to the leastsignificant bit, for the encoding. This means that the output of thedecoder 54 is (11110000) in the above-described example. Otherwise, ifthe voltage V_(fre) of the operating state signal S2 is determined to bethe maximum value V_(ref1) of the comparison voltage, for example, thedecoder 54 encodes the minimum digital data (00000000); if it isdetermined to be the minimum value V_(refn), for example, it encodes themaximum digital data (11111111); to generate the n-bit operating statedata D.

[0067] This operating state data D is input to the voltage outputcontrol section 60 which is configured of a digital-analog converter 62and a sample-and-hold circuit 64. Thus input operating state data D,which is n-bit digital data, is converted by the digital-analogconverter 62 to an analog voltage. Further, the analog voltage issampled by the operating-setting signal S_(SET1) at the sample-and-holdcircuit 64, and the level of the analog voltage is held when theoperating-setting period ends (when the operating-setting signalS_(SET1) switches from 1 to 0), to modify the basic voltage of theconstant voltage generation section 20 from the initial voltage toV_(B1). The constant voltage generation section modifies the level ofthe constant voltage V_(C1) based on the modified basic voltage V_(B1),as described previously. As a result, the first function block 30-1 issupplied with the constant voltage V_(C1) fitting to the operating statethereof, as the power voltage.

[0068] Signal waveforms used in the process of modifying the constantvoltages V_(C2) and V_(CN) by negative feedback for the second functionblock 30-2 and the Nth function block 30-N in the circuit of FIG. 1 areshown in FIGS. 5 and 6, respectively, in a similar manner to that ofFIG. 3.

[0069] In this case, the periods T₁, T₂, and T_(N) during which thecorresponding operation determination setting signals S_(SET1),S_(SET2)and S_(SETN) are active in FIGS. 3, 5, and 6 are set todifferent timings on the time axis. This ensures that a negativefeedback amplification circuit comprising the operating state detector40, the operating state encoding section 50, the voltage output controlsection 60, and the constant voltage generation section 20 can be usedin common by a plurality of function blocks which are the first to Nthfunction blocks 30-1 to 30-N.

[0070] It is clear from a comparison of FIGS. 3, 5, and 6 in this casethat, if the frequencies of the input signals S_(IN1), S_(IN2), andS_(INN) that are input to the first, second, and Nth function blocks30-1, 30-2, and 30-N are S_(fre1), S_(fre2), and S_(freN), respectively,their relationship is such that: S_(fre2)<S_(fre1)<S_(freN). Inaddition, the effective value (area under the rectangular waveform) ofthe input signal increases as the operating frequency decreases, so thatthe power consumed by the function block increases.

[0071] With this embodiment, if the power consumption of a functionblock is increasing, the constant voltage that is supplied theretodecreases, so that the power consumed thereby decreases.

[0072] The relationships between the peak voltage V_(P1) of theoperating state signal S2 of FIG. 3 and the peak voltages V_(P2) andV_(PN) of the operating state signal S2 of FIGS. 4 and 6 are such that:V_(PN)<V_(P1)<V_(P2). Thus the relationships between the basic voltagesV_(B1), V_(B2), and V_(BN) generates by the sample-and-hold circuit 64are V_(B2)<V_(B1)<V_(BN). This makes it possible to reduce the constantvoltage supplied to a function block in which the operating frequencyhas dropped, enabling a reduction in power consumption.

[0073] Second Embodiment

[0074] The timing chart of FIG. 7 shows the signal waveforms obtainedwhen the threshold voltages of MOS transistors that configure thesemiconductor integrated circuit 10 of FIG. 1 are different for eachfunction block, and the circuitry of FIGS. 1 and 2 is used to applynegative feedback, in a similar manner to that of FIG. 3.

[0075] In this case, if the threshold voltage of the MOS transistor ofthe first function block 30-1 is assumed to be V_(th1), the thresholdvoltage of the MOS transistor of the second function block 30-2 isassumed to be V_(th2), and the threshold voltage of the MOS transistorof the Nth function block 30-N is assumed to be V_(thN) therelationships between these threshold voltages are:V_(th2)<V_(th1)<V_(thN).

[0076] When the constant voltage V_(C1) of the first function block 30-1is modified by negative feedback, the threshold voltage of the MOStransistor is V_(th1), and thus the peak value of an integration signalS_(INTE1) from the integrator 42 is V_(P1). Similarly, when the constantvoltages VC₂ and V_(CN) of the second and Nth function blocks 30-2 and30-N are modified, the threshold voltages of the MOS transistors in eachblock are V_(th2) and V_(thN), and thus integration signals S_(INTE2)and S_(INTEN) from the integrator 42 are at V_(P2) and V_(PN),respectively.

[0077] With the previously described embodiment, the peak value of theinput signal S_(IN) is different if the frequency thereof is different,but with this embodiment, differences in the threshold voltages of theMOS transistors configuring the function blocks ensures that the peakvalues are still different, even if an input signal S_(IN) of the samefrequency shown in FIG. 7 is input to each of the function blocks 30-1,30-2, and 30-N. It should be noted that although only theoperating-setting signal S_(SET1) is shown to be active during theperiod T₁ in FIG. 7, the peak values V_(P2) and V_(PN) described aboveare detected in periods T₂ and T_(N) during which the operating-settingsignals S_(SET2) and S_(SETN) are active, respectively. Therelationships between these peak values is, as shown in FIG. 7, suchthat: V_(PN)<V_(P1)<V_(P2).

[0078] Since the threshold voltage of a MOS transistor changes dependingon factors present during the manufacturing process, therefore, therelationship of the threshold voltage V_(th) and the voltage V_(IN) ofthe input signal S_(IN) with respect to the on-resistance Ron of the MOStransistor when it is operating is: Ron=1/(K×V_(IN)−V_(th)). Thisconstant K is determined by the manufacturing process of thesemiconductor integrated circuit and the physical form of the MOStransistor. Thus, if the voltage VIN of the input signal S_(IN) is thesame and the constant K is fixed, the on-resistance Ron of the MOStransistor changes with variations in the threshold voltage V_(th)thereof. This means that the on-resistance Ron increases when thethreshold voltage V_(th) increases, and the on-resistance Ron decreaseswhen the threshold voltage V_(th) decreases. Thus the voltage amplitudeof the integration signal S_(INTE) changes as the output impedance ofthe signal that is input to the integrator 42 changes.

[0079] The relationship between the on-resistance Ron and V_(th) of theMOS transistor ensures that the relationships between the peak voltageV_(P1), the peak voltage V_(P2), and the peak voltage V_(PN) are, asmentioned previously: V_(PN)<V_(P1)<V_(P2).

[0080] In this embodiment too, the constant voltages V_(C1), V_(C2), andV_(CN) supplied to the corresponding function blocks 30-1, 30-2, and30-N are modified by negative feedback based on the basic voltagesV_(B1), V_(B2), and V_(BN) that are modified in accordance with the peakvoltages thereof, so that there is no variation in frequency responsespeed between the first to Nth function blocks 30-1 to 30-N, even whenan input signal S_(IN) of the same frequency is input to the functionblocks 30-1 to 30-N.

[0081] Third Embodiment

[0082] A block diagram of a circuit in accordance with a thirdembodiment of the present invention is shown in FIG. 8. The circuit ofFIG. 8 differs from the circuit shown in FIG. 2 in that a peak-to-peakdetector 70 is used instead of the peak detector 44 of FIG. 2.

[0083] This peak-to-peak detector 70 differs from the peak detector 44in that it holds the voltage amplitude of the integration signalS_(INTE1) in contrast to the peak detector 44 which detects and hold thepeak value of the integration signal S_(INTE1).

[0084] The timing chart of FIG. 9 shows the signal waveforms obtainedwhen the threshold voltages of MOS transistors that configure thesemiconductor integrated circuit 10 of FIG. 1 are different for eachfunction block, and the circuitry of FIGS. 1 and 8 is used to applynegative feedback.

[0085] The relationships between the threshold voltages of P-channel MOStransistors configuring the first, second, and Nth function blocks 30-1,30-2, and 30-N are such that: V_(thp2)<V_(tbp1)<V_(thpN).

[0086] In this case, the threshold voltage of the P-channel MOStransistor of the first function block 30-1 is V_(thp1), the thresholdvoltage of an N-channel MOS transistor is V_(thn1), and the voltageamplitude of the integration signal S_(INTE1) generated by theintegrator 44 is V_(pp1) (see FIG. 9).

[0087] The threshold voltage of the P-channel MOS transistor of thesecond function block 30-2 is V_(thp2), the threshold voltage of anN-channel MOS transistor is V_(thn2), and the voltage amplitude of theintegration signal S_(INTE2) generated by the integrator 44 is V_(pp2)(see FIG. 9).

[0088] The threshold voltage of the P-channel MOS transistor of the Nthfunction block 30-N is V_(thpN) the threshold voltage of an N-channelMOS transistor is V_(thnN) and the voltage amplitude of the integrationsignal S_(INTEN) generated by the integrator 44 is V_(ppN) (see FIG. 9).

[0089] When the relationships between these voltage amplitudes is, asshown in FIG. 9, such that: V_(ppN)<V_(pp2)<V_(pp1); the relationshipsbetween the basic voltages V_(B1), V_(B2), and V_(BN) that are eachgenerated by the sample-and-hold circuit 64 is: V_(B2) <V_(B1)<V_(BN);and the threshold voltages of each of the P-channel MOS transistors andN-channel MOS transistors are different for each function block; thereis no variation in frequency response speed between the function blocks,even when an input signal S_(IN) of the same frequency is input to thefunction blocks, in a similar manner to that exhibited by the secondembodiment.

[0090] This embodiment is particularly superior to the use of the peakdetector 44 of FIG. 2 in that, even if there are differences inamplitude between rise and fall of the initial integrated waveform, thevoltage amplitude of the integrated waveforms that are used in commoncan be detected accurately, as shown in FIG. 9 for the integrationsignal S_(INTE2).

[0091] Fourth Embodiment

[0092] A block diagram of electronic equipment that uses a semiconductorintegrated circuit having the previously described voltage controlsection is shown in FIG. 10.

[0093] This electronic equipment 310 is configured of a system controlsection 312, a specific function generation section 313, and asemiconductor integrated circuit 300 that are all driven by a powersource 311. The system control section 312 has the function ofcontrolling the entire system of the electronic equipment 310, such as amicroprocessor, bus control system, or memory control system. Thespecific function generation section 313 functions to provide specificcontrol over a device such as a data transfer device, an internal orexternal storage device, or a input-output device. The system controlsection 312 and the specific function generation section 313 areconnected by input-output signals 315, for inputting and outputtingsignals and data. The power source 311 supplies a power voltage 314 toall of structural elements of the electronic equipment 310.

[0094] The semiconductor integrated circuit 300 provided within theelectronic equipment 310 uses an internal power voltage control section302 to raise or lower the voltage of an internal constant-voltage source303 and thus modify the power voltage supplied to a group of functionblocks 304, when there is a change in the operating speed of an inputsignal 301 imparted thereto by the system control section 312 and thespecific function generation section 313. When the voltage that isoutput by the internal constant-voltage source 303 of the semiconductorintegrated circuit 300 is modified, the semiconductor integrated circuit300 generates a detection signal 305 and supplies it to the systemcontrol section 312 and the specific function generation section 313.This detection signal 305 is used to convey to the system controlsection 312 and the specific function generation section 313 theinstruction that the power consumption of the semiconductor integratedcircuit 300 is being controlled.

[0095] Note that the present invention is not limited to theabove-described embodiments and various other modifications thereof arepossible within the scope of the present invention. For example, theembodiment shown in FIG. 1 uses the low voltage generation section 20,the operating state detector 40, the operating state encoding section50, and the voltage output control section 60 in common for theplurality of function blocks 30-1 to 30-N, but these components could beprovided individually for each of these function blocks. Similarly, theembodiment of FIG. 1 has a configuration such that power is suppliedfrom one external power source 1 to the semiconductor integrated circuit10, but the present invention can also be applied to a semiconductorintegrated circuit in which different power voltages of, for example, 3V, 5 V, and so on are supplied from a plurality of external powersources. In such a case, it would be necessary to provide the samenumber of constant voltage generation sections as external powersources.

What is claimed is:
 1. A semiconductor integrated circuit comprising: atleast one constant voltage generation section for increasing ordecreasing a power voltage supplied from at least one external powersource, based on a basic voltage, to generate at least one constantvoltage; at least one function block to which is supplied said at leastone constant voltage generated by said at least one constant voltagegeneration section; at least one operating state detection section forgenerating a second signal indicating an operating state of said atleast one function block, based on a first signal including operatingspeed information of said at least one function block; at least oneoperating state encoding section for encoding an operating state of saidfunction block to generate operating state date, based on said secondsignal; and at least one voltage output control section for modifyingsaid basic voltage of said at least one constant voltage generationsection, based on said operating state data.
 2. The semiconductorintegrated circuit as defined in claim 1 , wherein: an operating-settingsignal is input to said at least one function block, and said at leastone function block supplies said first signal to said at least oneoperating state detection section when said operating-setting signal isactive.
 3. The semiconductor integrated circuit as defined in claim 2 ;wherein: one each of said at least one operating state detectionsection, said at least one operating state encoding section, said atleast one voltage output control section, and said at least one constantvoltage generation section is provided in common for said plurality offunction blocks; and said operating-setting signal becomes active atdifferent timings along the time axis for each of said plurality offunction blocks.
 4. The semiconductor integrated circuit as defined inclaim 1 , wherein: said at least one voltage output control sectioncomprises: a digital-analog converter for performing a digital-to-analogconversion on said operating state data; and a sample-and-hold circuitfor sampling an output of said digital-analog converter based on saidoperating-setting signal, and generating said basic voltage.
 5. Thesemiconductor integrated circuit as defined in claim 1 , wherein: saidat least one operating state detection section comprises: an integratorfor integrating said first signal; and a peak detector for detecting apeak value of an output of said integrator, and holding said peak valueas said second signal.
 6. The semiconductor integrated circuit asdefined in claim 1 , wherein: said at least one operating statedetection section comprises: an integrator for integrating said firstsignal; and a voltage amplitude detector for detecting a voltageamplitude of an output of said integrator, and holding said voltageamplitude as said second signal.
 7. The semiconductor integrated circuitas defined in claim 1 , wherein: said at least one operating stateencoding section comprises: a plurality of comparators for comparing thevoltage level of said second signal with each of a plurality ofreference voltage levels; and an encoder for encoding outputs of saidplurality of comparators.
 8. The semiconductor integrated circuit asdefined in claim 7 , further comprising: a plurality of voltage-dividingresistors for dividing said constant voltage from said at least oneconstant voltage generation section, to create said plurality ofreference voltage levels.
 9. A semiconductor integrated circuitcomprising: at least one constant voltage generation section forincreasing or decreasing a power voltage supplied from at least oneexternal power source, based on a basic voltage, to generate at leastone constant voltage; at least one function block to which is suppliedsaid at least one constant voltage generated by said at least oneconstant voltage generation section; at least one frequency-voltageconverter for converting an actual operating frequency of said at leastone function block into a voltage level; at least one operating stateencoding section for encoding an operating state of said function blockto generate operating state data, based on the output voltage of saidfrequency-voltage converter; and at least one voltage output controlsection for modifying said basic voltage of said at least one constantvoltage generation section, based on said operating state data.
 10. Thesemiconductor integrated circuit as defined in claim 9 , wherein: saidfrequency-voltage converter converts a frequency of an input signal thatis input to said at least one function block into a voltage level. 11.The semiconductor integrated circuit as defined in claim 10 , wherein:an operating-setting signal is input to said at least one functionblock, and said at least one function block supplies said input signalto said frequency-voltage converter when said operating-setting signalis active.
 12. The semiconductor integrated circuit as defined in claim11 , wherein: one each of said at least one frequency-voltage converter,said at least one operating state encoding section, said at least onevoltage output control section, and said at least one constant voltagegeneration section is provided in common for said plurality of functionblocks; and said operating-setting signal becomes active at differenttimings along the time axis for each of said plurality of functionblocks.
 13. Electronic equipment comprising the semiconductor integratedcircuit as defined in claim 1 .